Referring to FIG. 1, a diagram of a conventional layout 10 for an application specific integrated circuit (ASIC) is shown. Generation of the conventional layout 10 involves placing and routing numerous standard cells 12a-12n. Power is provided to the standard cells 12a-12n by way of a horizontal series of power rails 14a-14k. Every other power rail 14a-14k alternatively carries a power and a ground. Electrical power is distributed to the rails 14a-14k by a power mesh 16. The power mesh 16 conventionally forms a series of vertical power mesh routes 16a-16d. Every other power mesh route 16a-16d alternatively carries the power and the ground. Via arrays 18a-18x connect the power rails 14a-14k to the appropriate power mesh routes 16a-16d. 
An individual via size and a number of vias in the arrays 18a-18x connecting the power rails 14a-14k up to the power mesh routes 16a-16d is conventionally calculated by a tool based on an overall current flow (i.e., electromigration requirements or current density limits). As a result, the via size and the number of vias in the via arrays 18a-18x is the same over the entire circuit layout. The tool does not consider a number or kind of cells 12a-12n in each specific row segment or how much power is really used in the row segment. As shown in FIG. 1, different numbers of standard cells 12a-12n are placed in different row segments between pairs of power mesh routes 16a-16d. However, the via arrays 18a-18x connecting the power mesh routes 16a-16d to the power rails 14a-14k are all the same.
The volume occupied by the vias between the power rails 14a-14k up to the power mesh routes 16a-16d block routing channels in all metal layers that the vias intersect. Routing resources are wasted because regions of low standard cell density use less power than regions of high standard cell density. After automatic routing has been completed, unnecessary vias in the via arrays 18a-18x that were initially inserted to handle a maximum current flow are conventionally removed manually by design engineers. The design engineers can also manually reduce the vias in congested areas, but removing the vias can cause IR-drops and electromigration problems. Checking for IR-drop problems and electromigration problems is usually done later in a conventional design flow.